Conventional floating-point standards, such as the ANSI/IEEE Standard 754-1985 IEEE Standard for Binary Floating-Point Arithmetic ("IEEE standard") require that a status flag be provided for each type of exception that can occur. For example, a status flag must be provided for data overflow. When set, the status flag indicates that the specified exception has occurred.
Certain conventional standards, such as the IEEE standard, also specify that the user shall be able to test and to alter the status flags individually. Furthermore, the IEEE standard specifies that the user should be able to save and restore all status flags at one time.
Some conventional systems utilize a floating-point status and control register ("FPSCR") to store the status flags. The FPSCR is controlled by FPSCR instructions. FPSCR read instructions allow the system to read, or move data from, the FPSCR. Similarly, FPSCR write instructions allow the system to move data to the FPSCR. For example, the FPSCR may be controlled by a set of six FPSCR instructions. Four of these instructions write or move data to the FPSCR. The two of remaining FPSCR instructions read or move data from the FPSCR.
Conventional floating-point systems implement the FPSCR instructions by wholly placing the FPSCR instructions in a floating-point execution unit pipeline. However, the FPSCR instructions are typically executed by FPSCR execution logic placed in series with the pipeline. In other words, the FPSCR execution logic is typically placed after the floating-point execution logic. Nevertheless, additional dedicated FPSCR logic must be placed in the pipeline to allow the FPSCR instruction to pass through the pipeline.
If the pipelines of the conventional system are symmetric, the dedicated FPSCR logic for passing the FPSCR instruction through the pipeline is provided in both pipelines. A system having symmetric pipelines is simpler to design since pipelines are simply replicated. However, since FPSCR instructions occur more rarely than floating-point instructions, the dedicated FPSCR logic in the pipeline will be largely unused. In addition, because FPSCR instructions still require serialization, the additional dedicated FPSCR logic will provide little performance gain.
Where symmetric pipelines are used, each symmetric pipeline may have is own FPSCR execution logic provided after the pipeline's floating-point execution logic. However, the pipelines may also share FPSCR execution logic placed after both floating-point execution units. There is a disadvantage to having symmetric floating-point execution units with only one FPSCR execution logic in series with both pipelines. That is, the FPSCR execution logic is typically more complex because FPSCR instructions can be input to the FPSCR execution logic from either pipeline. Therefore, the FPSCR execution logic must be able to determine which pipeline provides the FPSCR instruction and account for any timing differences.
Other conventional systems use non-symmetric floating-point pipelines. In such systems, an FPSCR instruction is issued to only certain pipelines. Thus, only these pipelines contain dedicated FPSCR logic for passing the FPSCR instruction through the pipeline. Because all FPSCR instructions are passed through a single pipeline, the dedicated FPSCR logic in the pipeline is used more frequently than dedicated FPSCR logic in each of the symmetric pipelines would be used. In addition, because only a limited number of pipelines, such as a single pipeline, provide the FPSCR instruction to the FPSCR execution logic, the FPSCR execution logic is less complex. However, as previously stated, non-symmetric pipelines add complexity to the design because the system cannot be provided simply by duplicating a single execution pipeline.
FPSCR instruction execution may cause multi-cycle delays, regardless of whether a floating-point execution unit pipelines in the system are symmetric. This is because an FPSCR instruction is a serializing instruction. A serializing instruction is one which must have at least portion of the pipeline free in order to run correctly. An FPSCR instruction is typically followed by a series of floating-point instructions. An FPSCR instruction is serializing because it may alter settings in the FPSCR upon which subsequent floating-point instructions depend. As a result, the FPSCR instruction requires that the portion of the pipeline behind the FPSCR instruction be free during execution. If this portion of the pipeline is not free, subsequent instructions may access incorrect settings in the FPSCR.
Because stages in the pipeline must be kept open during execution of the FPSCR instruction and floating-point pipelines are typically deep, a multi-cycle delay is introduced by each FPSCR instruction. Thus, although the FPSCR instruction can be executed relatively quickly by the FPSCR execution logic, delays are introduced as the FPSCR instruction passes through the pipeline. For conventional floating-point pipelines which have many stages, this delay is greater.
Accordingly, what is needed is a system and method for executing FPSCR instructions having reduced delay. It would also be beneficial if the method allowed for symmetric floating-point execution pipelines, making design of pipelines simpler. The present invention addresses such a need.